Computer Organization & Architecture_MCA_1st Sem
Computer Organization & Architecture (MCA 1st Semester)
MCQs 1–50
1. Computer Architecture refers to:
A) Physical components of computer
B) Functional behavior and design of a computer system
C) Software development process
D) Database structure
Answer: B
2. Computer Organization deals with:
A) Hardware implementation details
B) Programming languages
C) Operating systems only
D) Network topology
Answer: A
3. The brain of the computer is:
A) RAM
B) Hard Disk
C) CPU
D) ROM
Answer: C
4. CPU stands for:
A) Central Process Unit
B) Central Processing Unit
C) Computer Processing Unit
D) Core Processing Unit
Answer: B
5. The Arithmetic Logic Unit (ALU) performs:
A) Input operations
B) Arithmetic and logical operations
C) Storage operations
D) Networking operations
Answer: B
6. The Control Unit (CU) is responsible for:
A) Arithmetic calculations
B) Controlling execution of instructions
C) Data storage
D) Printing output
Answer: B
7. Which register stores the address of the next instruction?
A) IR
B) MAR
C) PC
D) MDR
Answer: C
8. PC stands for:
A) Program Counter
B) Process Counter
C) Primary Counter
D) Program Code
Answer: A
9. Which register holds the current instruction?
A) IR
B) MAR
C) PC
D) ACC
Answer: A
10. IR stands for:
A) Instruction Register
B) Internal Register
C) Input Register
D) Instruction Recorder
Answer: A
11. Which register stores memory addresses?
A) MDR
B) MAR
C) ACC
D) PC
Answer: B
12. MAR stands for:
A) Memory Address Register
B) Main Address Register
C) Memory Access Register
D) Main Access Register
Answer: A
13. MDR stands for:
A) Memory Data Register
B) Main Data Register
C) Memory Device Register
D) Main Device Register
Answer: A
14. The accumulator is used to:
A) Store intermediate results
B) Store instructions
C) Store addresses
D) Control execution
Answer: A
15. Which cycle fetches instructions from memory?
A) Decode Cycle
B) Execute Cycle
C) Fetch Cycle
D) Store Cycle
Answer: C
16. The instruction cycle consists of:
A) Fetch and Execute
B) Input and Output
C) Read and Write
D) Load and Store
Answer: A
17. A microprocessor is:
A) CPU on a single chip
B) Memory chip
C) Input device
D) Output device
Answer: A
18. Which generation introduced microprocessors?
A) First
B) Second
C) Third
D) Fourth
Answer: D
19. The basic unit of information is:
A) Byte
B) Bit
C) Word
D) Nibble
Answer: B
20. One byte contains:
A) 4 bits
B) 8 bits
C) 16 bits
D) 32 bits
Answer: B
21. Which number system is used internally by computers?
A) Decimal
B) Binary
C) Octal
D) Hexadecimal
Answer: B
22. Binary number 1010 equals decimal:
A) 8
B) 9
C) 10
D) 12
Answer: C
23. Hexadecimal number system uses:
A) Base 2
B) Base 8
C) Base 10
D) Base 16
Answer: D
24. Decimal 15 in hexadecimal is:
A) E
B) F
C) 10
D) A
Answer: B
25. Which code is commonly used for alphanumeric characters?
A) ASCII
B) BCD
C) Gray Code
D) Excess-3
Answer: A
26. ASCII uses:
A) 7 bits
B) 8 bits
C) 16 bits
D) 32 bits
Answer: A
27. Unicode was developed to:
A) Replace memory
B) Support multiple languages
C) Increase processor speed
D) Reduce storage
Answer: B
28. Which code changes only one bit between successive numbers?
A) ASCII
B) BCD
C) Gray Code
D) EBCDIC
Answer: C
29. BCD stands for:
A) Binary Coded Decimal
B) Binary Code Digit
C) Bit Coded Decimal
D) Binary Control Data
Answer: A
30. Logic gates are implemented using:
A) Electronic Circuits
B) Databases
C) Software only
D) Operating Systems
Answer: A
31. AND gate produces output 1 when:
A) Any input is 1
B) All inputs are 1
C) All inputs are 0
D) Any input is 0
Answer: B
32. OR gate produces output 1 when:
A) All inputs are 1
B) Any input is 1
C) All inputs are 0
D) Inputs are equal
Answer: B
33. NOT gate is also called:
A) Inverter
B) Encoder
C) Decoder
D) Multiplexer
Answer: A
34. XOR gate produces output 1 when:
A) Inputs are same
B) Inputs are different
C) All inputs are 1
D) All inputs are 0
Answer: B
35. NAND gate is called:
A) Universal Gate
B) Special Gate
C) Exclusive Gate
D) Control Gate
Answer: A
36. NOR gate is:
A) Arithmetic Gate
B) Universal Gate
C) Sequential Gate
D) Memory Gate
Answer: B
37. A half adder adds:
A) Two bits
B) Three bits
C) Four bits
D) Eight bits
Answer: A
38. A full adder adds:
A) Two bits only
B) Two bits and carry input
C) Four bits
D) Eight bits
Answer: B
39. A decoder converts:
A) Binary to Decimal Output Lines
B) Decimal to Binary
C) Analog to Digital
D) Digital to Analog
Answer: A
40. A multiplexer is:
A) Many-to-One Device
B) One-to-Many Device
C) Memory Device
D) Control Device
Answer: A
41. Demultiplexer performs:
A) Many-to-One
B) One-to-Many
C) Data Storage
D) Data Compression
Answer: B
42. Flip-flops are used in:
A) Memory Circuits
B) Printers
C) Monitors
D) Hard Disks
Answer: A
43. Which flip-flop has no invalid state?
A) SR
B) JK
C) D
D) T
Answer: B
44. A register is:
A) Group of Flip-Flops
B) Logic Gate
C) Input Device
D) Output Device
Answer: A
45. Shift registers are used for:
A) Data Transfer
B) Printing
C) Networking
D) Display Output
Answer: A
46. Counter is a:
A) Sequential Circuit
B) Combinational Circuit
C) Input Device
D) Memory Unit
Answer: A
47. Asynchronous counters are also called:
A) Ripple Counters
B) Ring Counters
C) Synchronous Counters
D) Binary Counters
Answer: A
48. Which memory is volatile?
A) ROM
B) EEPROM
C) RAM
D) Flash Memory
Answer: C
49. ROM is:
A) Read Only Memory
B) Random Only Memory
C) Read Open Memory
D) Random Open Memory
Answer: A
50. RAM stands for:
A) Read Access Memory
B) Random Access Memory
C) Rapid Access Memory
D) Random Available Memory
Answer: B
Computer Organization & Architecture (MCA 1st Semester)
MCQs 51–100
51. Which memory is non-volatile?
A) RAM
B) Cache
C) ROM
D) Register
Answer: C
52. Cache memory is used to:
A) Increase storage capacity
B) Speed up memory access
C) Replace RAM
D) Store backup data
Answer: B
53. Cache memory is located:
A) Near CPU
B) Inside Hard Disk
C) Inside Keyboard
D) In Monitor
Answer: A
54. Which memory has the fastest access time?
A) Hard Disk
B) RAM
C) Cache
D) Optical Disk
Answer: C
55. The memory hierarchy is based on:
A) Cost, Speed, and Capacity
B) Color and Size
C) Voltage only
D) Processor Type only
Answer: A
56. Which memory is the fastest?
A) Registers
B) RAM
C) Cache
D) ROM
Answer: A
57. SRAM stands for:
A) Static Random Access Memory
B) Standard RAM
C) Serial RAM
D) System RAM
Answer: A
58. DRAM stands for:
A) Dynamic Random Access Memory
B) Digital RAM
C) Direct RAM
D) Dynamic Read Access Memory
Answer: A
59. SRAM is generally:
A) Slower than DRAM
B) Faster than DRAM
C) Equal to DRAM
D) Non-volatile
Answer: B
60. DRAM requires:
A) No Refreshing
B) Periodic Refreshing
C) Rebooting
D) Formatting
Answer: B
61. Cache memory generally uses:
A) DRAM
B) SRAM
C) ROM
D) EEPROM
Answer: B
62. Main memory generally uses:
A) SRAM
B) DRAM
C) ROM
D) Flash Memory
Answer: B
63. Virtual memory is:
A) Physical Memory
B) Extension of Main Memory using Disk Storage
C) Cache Memory
D) Register Memory
Answer: B
64. Paging is used in:
A) Virtual Memory Management
B) Input Devices
C) Output Devices
D) Registers
Answer: A
65. A page fault occurs when:
A) CPU is damaged
B) Required page is not in main memory
C) Cache is full
D) Hard disk fails
Answer: B
66. The smallest addressable memory unit is:
A) Word
B) Byte
C) Block
D) Register
Answer: B
67. A memory address identifies:
A) Data Location
B) CPU Type
C) Instruction Set
D) I/O Device
Answer: A
68. Which bus carries memory addresses?
A) Data Bus
B) Address Bus
C) Control Bus
D) System Bus
Answer: B
69. Which bus carries actual data?
A) Data Bus
B) Address Bus
C) Control Bus
D) Memory Bus
Answer: A
70. Which bus carries control signals?
A) Address Bus
B) Data Bus
C) Control Bus
D) Local Bus
Answer: C
71. System bus consists of:
A) Data Bus
B) Address Bus
C) Control Bus
D) All of these
Answer: D
72. The width of the address bus determines:
A) Processing Speed
B) Maximum Memory Capacity
C) CPU Frequency
D) Cache Size
Answer: B
73. A 16-bit address bus can address:
A) 64 KB Locations
B) 32 KB Locations
C) 16 KB Locations
D) 128 KB Locations
Answer: A
74. Instruction Set Architecture (ISA) defines:
A) Hardware Manufacturing
B) Programmer Visible Architecture
C) Monitor Resolution
D) Power Supply Design
Answer: B
75. An instruction consists of:
A) Opcode and Operand
B) Data and Address Only
C) Bus and Register
D) CPU and Memory
Answer: A
76. Opcode specifies:
A) Address Location
B) Operation to be Performed
C) Memory Size
D) CPU Speed
Answer: B
77. Operand specifies:
A) Operation
B) Data or Address
C) Bus Width
D) Cache Size
Answer: B
78. Addressing mode specifies:
A) Memory Size
B) Way of Accessing Operand
C) CPU Clock Speed
D) Bus Width
Answer: B
79. Immediate addressing mode stores:
A) Operand inside instruction
B) Operand in memory
C) Operand in cache
D) Operand in hard disk
Answer: A
80. Direct addressing mode contains:
A) Register Number
B) Effective Memory Address
C) Immediate Data
D) Cache Block
Answer: B
81. Indirect addressing mode requires:
A) One memory access
B) Two memory accesses
C) No memory access
D) Cache access only
Answer: B
82. Register addressing mode uses:
A) Main Memory
B) CPU Registers
C) Hard Disk
D) Virtual Memory
Answer: B
83. Indexed addressing is useful for:
A) Arrays
B) Printers
C) Compilers
D) Keyboards
Answer: A
84. Stack is a:
A) FIFO Structure
B) LIFO Structure
C) Memory Bus
D) Cache Unit
Answer: B
85. PUSH operation:
A) Removes Data from Stack
B) Adds Data to Stack
C) Copies Stack
D) Clears Stack
Answer: B
86. POP operation:
A) Adds Data to Stack
B) Removes Data from Stack
C) Clears Stack
D) Encrypts Stack
Answer: B
87. Which register points to the top of stack?
A) PC
B) IR
C) SP
D) MAR
Answer: C
88. SP stands for:
A) Stack Pointer
B) System Pointer
C) Storage Pointer
D) Special Pointer
Answer: A
89. Input devices are used to:
A) Enter Data into Computer
B) Display Data
C) Store Data
D) Process Data
Answer: A
90. Output devices are used to:
A) Store Data
B) Display Results
C) Process Instructions
D) Transfer Data
Answer: B
91. I/O stands for:
A) Input/Output
B) Internal Output
C) Input Operation
D) Internal Operation
Answer: A
92. Programmed I/O requires:
A) CPU Intervention
B) No CPU Intervention
C) DMA Only
D) Cache Only
Answer: A
93. Interrupt-driven I/O improves:
A) CPU Utilization
B) Memory Size
C) Cache Size
D) Hard Disk Speed
Answer: A
94. DMA stands for:
A) Direct Memory Access
B) Dynamic Memory Access
C) Direct Main Access
D) Data Memory Access
Answer: A
95. DMA allows:
A) CPU to Access Memory Only
B) I/O Device to Transfer Data Directly to Memory
C) Cache Access Only
D) Register Access Only
Answer: B
96. Interrupt is a:
A) Signal Requesting CPU Attention
B) Memory Device
C) Storage Unit
D) Register Type
Answer: A
97. Interrupt Service Routine (ISR) is:
A) Program Handling Interrupts
B) Memory Unit
C) CPU Register
D) Bus Controller
Answer: A
98. Priority Interrupts are used when:
A) Multiple Interrupts Occur Simultaneously
B) Memory Fails
C) Cache Overflows
D) CPU Stops Working
Answer: A
99. Polling is:
A) CPU Continuously Checking Device Status
B) Memory Access Method
C) Cache Replacement Policy
D) Instruction Format
Answer: A
100. The main objective of computer organization is:
A) Efficient Hardware Utilization and Performance
B) Increase Monitor Size
C) Reduce Keyboard Usage
D) Eliminate Memory
Answer: A
Computer Organization & Architecture (MCA 1st Semester)
MCQs 101–150
101. CPU performance is mainly affected by:
A) Clock Speed
B) Number of Instructions
C) CPI (Cycles Per Instruction)
D) All of these
Answer: D
102. Clock speed is measured in:
A) Bytes
B) Hertz (Hz)
C) Volts
D) Ohms
Answer: B
103. 1 GHz equals:
A) 10⁶ Hz
B) 10⁷ Hz
C) 10⁸ Hz
D) 10⁹ Hz
Answer: D
104. Throughput refers to:
A) Time taken per task
B) Number of tasks completed per unit time
C) Memory size
D) Cache size
Answer: B
105. Latency refers to:
A) Delay before completion of a task
B) CPU frequency
C) Bus width
D) Register count
Answer: A
106. Pipelining improves:
A) Instruction Throughput
B) Memory Capacity
C) Hard Disk Size
D) Power Supply
Answer: A
107. Instruction pipelining divides execution into:
A) Stages
B) Registers
C) Memories
D) Devices
Answer: A
108. The first stage of a pipeline is:
A) Execute
B) Decode
C) Fetch
D) Write Back
Answer: C
109. Pipeline hazards reduce:
A) CPU Performance
B) Memory Size
C) Bus Width
D) Storage Capacity
Answer: A
110. Structural hazards occur due to:
A) Resource Conflicts
B) Data Dependency
C) Branch Instructions
D) Memory Failure
Answer: A
111. Data hazards occur because of:
A) Resource Sharing
B) Data Dependencies
C) Cache Misses
D) Interrupts
Answer: B
112. Control hazards are mainly caused by:
A) Arithmetic Operations
B) Branch Instructions
C) Memory Access
D) Registers
Answer: B
113. Branch prediction is used to:
A) Increase Memory Size
B) Reduce Control Hazard Impact
C) Increase Cache Size
D) Improve Storage
Answer: B
114. Superscalar processors can:
A) Execute Multiple Instructions per Clock Cycle
B) Store More Data
C) Increase RAM Size
D) Replace Cache
Answer: A
115. Parallel processing means:
A) Executing Multiple Tasks Simultaneously
B) Increasing Storage
C) Reducing Memory
D) Decreasing Clock Speed
Answer: A
116. Flynn's classification is based on:
A) Memory Types
B) Instruction and Data Streams
C) Processor Frequency
D) Bus Architecture
Answer: B
117. SISD stands for:
A) Single Instruction Single Data
B) Single Input Single Data
C) Simple Instruction Single Data
D) Sequential Instruction Single Data
Answer: A
118. Traditional sequential computers belong to:
A) SISD
B) SIMD
C) MISD
D) MIMD
Answer: A
119. SIMD stands for:
A) Single Instruction Multiple Data
B) Simple Instruction Multiple Data
C) Single Input Multiple Data
D) System Instruction Multiple Data
Answer: A
120. GPUs commonly use:
A) SISD
B) SIMD
C) MISD
D) None
Answer: B
121. MIMD stands for:
A) Multiple Instruction Multiple Data
B) Multiple Input Multiple Data
C) Main Instruction Multiple Data
D) Mixed Instruction Multiple Data
Answer: A
122. Multiprocessor systems usually follow:
A) MIMD Architecture
B) SISD Architecture
C) MISD Architecture
D) Analog Architecture
Answer: A
123. MISD stands for:
A) Multiple Instruction Single Data
B) Multiple Input Single Data
C) Main Instruction Single Data
D) Multiple Internal Single Data
Answer: A
124. Which Flynn category is least common?
A) SISD
B) SIMD
C) MISD
D) MIMD
Answer: C
125. A multicore processor contains:
A) Multiple CPUs on a Single Chip
B) Multiple Hard Disks
C) Multiple Monitors
D) Multiple Keyboards
Answer: A
126. Dual-core processor contains:
A) One Core
B) Two Cores
C) Four Cores
D) Eight Cores
Answer: B
127. Quad-core processor contains:
A) Two Cores
B) Four Cores
C) Six Cores
D) Eight Cores
Answer: B
128. Hyper-threading allows:
A) One Core to Execute Multiple Threads
B) Memory Expansion
C) Cache Replacement
D) Hard Disk Access
Answer: A
129. A thread is:
A) Lightweight Process
B) Memory Unit
C) Register
D) Bus Line
Answer: A
130. Multiprocessing improves:
A) Performance and Reliability
B) Monitor Resolution
C) Keyboard Speed
D) Disk Capacity
Answer: A
131. Shared-memory multiprocessors use:
A) Common Memory
B) Separate Memory Only
C) No Memory
D) Virtual Memory Only
Answer: A
132. Distributed systems use:
A) Shared Cache
B) Independent Memories
C) Single Processor
D) Single Register
Answer: B
133. Amdahl's Law is used to:
A) Measure Performance Improvement
B) Increase Memory
C) Reduce Cache Misses
D) Design Registers
Answer: A
134. According to Amdahl's Law, speedup is limited by:
A) Parallel Portion
B) Sequential Portion
C) Cache Size
D) Bus Width
Answer: B
135. RISC stands for:
A) Reduced Instruction Set Computer
B) Rapid Instruction Set Computer
C) Reduced Internal System Computer
D) Register Instruction Set Computer
Answer: A
136. CISC stands for:
A) Complex Instruction Set Computer
B) Central Instruction Set Computer
C) Complex Internal System Computer
D) Core Instruction Set Computer
Answer: A
137. RISC architecture uses:
A) Simple Instructions
B) Complex Instructions
C) Long Instruction Cycles
D) Large Microcode
Answer: A
138. CISC architecture emphasizes:
A) Simpler Hardware
B) Complex Instructions
C) Fewer Addressing Modes
D) Fixed-Length Instructions
Answer: B
139. ARM processors are based on:
A) RISC
B) CISC
C) Hybrid Only
D) Analog Design
Answer: A
140. Intel x86 architecture is generally:
A) RISC
B) CISC
C) MISD
D) SIMD
Answer: B
141. Microprogrammed control unit uses:
A) Microinstructions
B) Hardwired Logic Only
C) Cache Memory
D) Virtual Memory
Answer: A
142. Hardwired control unit is:
A) Faster than Microprogrammed Control
B) Slower than Microprogrammed Control
C) Equal in Speed
D) Memory Based
Answer: A
143. Machine cycle refers to:
A) CPU Operation Cycle
B) Memory Refresh Cycle
C) Hard Disk Rotation
D) Bus Transfer Only
Answer: A
144. CPI stands for:
A) Cycles Per Instruction
B) Computer Performance Index
C) Central Processing Instruction
D) Control Program Index
Answer: A
145. Lower CPI indicates:
A) Better Performance
B) Worse Performance
C) More Memory Usage
D) Less Cache
Answer: A
146. Benchmark programs are used to:
A) Evaluate Computer Performance
B) Increase Memory
C) Design Registers
D) Manage Storage
Answer: A
147. MIPS stands for:
A) Million Instructions Per Second
B) Multiple Instructions Per Second
C) Memory Instructions Per Second
D) Machine Index Processing Speed
Answer: A
148. FLOPS measures:
A) Floating Point Operations Per Second
B) Fixed Logic Operations Per Second
C) File Operations Per Second
D) Fast Logic Operations Per Second
Answer: A
149. Supercomputers are commonly evaluated using:
A) FLOPS
B) CPI
C) Bytes
D) Cache Blocks
Answer: A
150. The primary goal of modern computer architecture is:
A) Higher Performance with Lower Power Consumption
B) Larger Monitors
C) More Keyboards
D) Fewer Instructions Only
Answer: A
Computer Organization & Architecture (MCA 1st Semester)
MCQs 151–200
151. Cache mapping determines:
A) How cache lines correspond to main memory blocks
B) CPU clock speed
C) Number of registers
D) Disk capacity
Answer: A
152. Which cache mapping technique is simplest?
A) Associative Mapping
B) Set-Associative Mapping
C) Direct Mapping
D) Virtual Mapping
Answer: C
153. In direct mapping, a memory block can be placed:
A) Anywhere in cache
B) In a specific cache line only
C) In two cache lines
D) In any set
Answer: B
154. Associative mapping allows:
A) Fixed placement
B) Placement in any cache line
C) Placement in one set only
D) No placement
Answer: B
155. Set-associative mapping is a combination of:
A) Direct and Associative Mapping
B) RAM and ROM
C) CPU and Memory
D) Cache and Disk
Answer: A
156. Cache hit occurs when:
A) Data is found in cache
B) Data is not found in cache
C) Memory fails
D) CPU stops
Answer: A
157. Cache miss occurs when:
A) Data is available in cache
B) Data is not available in cache
C) Cache is empty
D) CPU is idle
Answer: B
158. Hit ratio is:
A) Hits / Total Memory Accesses
B) Misses / Hits
C) CPU Time / Memory Time
D) Cache Size / RAM Size
Answer: A
159. Higher cache hit ratio means:
A) Better Performance
B) Lower Performance
C) More Disk Access
D) Less CPU Usage
Answer: A
160. Cache replacement policies are required in:
A) Direct Mapping
B) Associative and Set-Associative Mapping
C) RAM
D) Registers
Answer: B
161. FIFO replacement policy stands for:
A) First In First Out
B) Fast In Fast Out
C) First Instruction First Out
D) Fixed In Fixed Out
Answer: A
162. LRU stands for:
A) Least Recently Used
B) Last Recently Used
C) Least Read Unit
D) Last Read Unit
Answer: A
163. Which replacement policy generally provides better performance?
A) FIFO
B) Random
C) LRU
D) Direct
Answer: C
164. Write-through cache policy:
A) Updates cache and main memory simultaneously
B) Updates cache only
C) Updates memory only
D) Deletes cache data
Answer: A
165. Write-back cache policy:
A) Updates memory immediately
B) Updates memory only when block is replaced
C) Never updates memory
D) Updates registers only
Answer: B
166. Virtual memory provides:
A) Larger logical memory than physical memory
B) Faster CPU
C) Larger cache
D) More registers
Answer: A
167. Virtual memory is usually implemented using:
A) Hard Disk/SSD
B) Registers
C) Cache
D) ROM
Answer: A
168. The address generated by CPU is called:
A) Physical Address
B) Virtual Address
C) Cache Address
D) Bus Address
Answer: B
169. The actual memory location is called:
A) Logical Address
B) Virtual Address
C) Physical Address
D) Register Address
Answer: C
170. Address translation is performed by:
A) MMU
B) ALU
C) CU
D) Cache Controller
Answer: A
171. MMU stands for:
A) Memory Management Unit
B) Main Memory Unit
C) Machine Management Unit
D) Memory Mapping Unit
Answer: A
172. Paging eliminates:
A) External Fragmentation
B) Internal Fragmentation
C) CPU Delays
D) Cache Misses
Answer: A
173. Segmentation divides memory into:
A) Fixed-Size Pages
B) Variable-Size Segments
C) Cache Blocks
D) Registers
Answer: B
174. TLB stands for:
A) Translation Lookaside Buffer
B) Transfer Lookaside Buffer
C) Temporary Logic Buffer
D) Translation Logic Block
Answer: A
175. TLB is used to:
A) Speed up address translation
B) Increase RAM size
C) Improve CPU frequency
D) Replace cache
Answer: A
176. Associative memory is also called:
A) Content Addressable Memory (CAM)
B) Dynamic Memory
C) Static Memory
D) Virtual Memory
Answer: A
177. Associative memory searches data by:
A) Address
B) Content
C) Register Number
D) Cache Block
Answer: B
178. RAID stands for:
A) Redundant Array of Independent Disks
B) Random Access Independent Disks
C) Rapid Access Integrated Disks
D) Redundant Access Internal Disks
Answer: A
179. RAID improves:
A) Reliability and Performance
B) CPU Speed
C) Register Size
D) Instruction Count
Answer: A
180. RAID 0 provides:
A) Mirroring
B) Striping
C) Parity
D) Backup Only
Answer: B
181. RAID 1 uses:
A) Striping
B) Mirroring
C) Parity
D) Compression
Answer: B
182. RAID 5 uses:
A) Mirroring Only
B) Distributed Parity
C) No Redundancy
D) Compression
Answer: B
183. Multiprocessor systems contain:
A) Multiple CPUs
B) Multiple Monitors
C) Multiple Keyboards
D) Multiple Disks Only
Answer: A
184. Tightly coupled systems share:
A) Memory
B) Keyboard
C) Monitor
D) Printer
Answer: A
185. Loosely coupled systems communicate through:
A) Network Links
B) Shared Registers
C) Cache Only
D) ALU Only
Answer: A
186. SIMD architecture is suitable for:
A) Scientific Calculations
B) Data Parallel Tasks
C) Graphics Processing
D) All of these
Answer: D
187. Vector processors operate on:
A) Single Data Item
B) Entire Data Vectors
C) Memory Blocks
D) Registers Only
Answer: B
188. GPU stands for:
A) General Processing Unit
B) Graphics Processing Unit
C) Global Processing Unit
D) Graphic Program Unit
Answer: B
189. GPUs are optimized for:
A) Sequential Processing
B) Parallel Processing
C) Storage Management
D) Disk Operations
Answer: B
190. Multithreading allows:
A) Multiple Threads in One Process
B) Multiple CPUs Only
C) Multiple Monitors
D) Multiple Disks
Answer: A
191. Symmetric Multiprocessing (SMP) means:
A) All processors are equal
B) One processor controls others
C) No memory sharing
D) Only one processor works
Answer: A
192. Asymmetric Multiprocessing (AMP) means:
A) All processors equal
B) One master processor controls others
C) Shared cache only
D) Virtual processing
Answer: B
193. Cluster computing consists of:
A) Multiple Connected Computers Working Together
B) Multiple Registers
C) Multiple Buses
D) Multiple Caches
Answer: A
194. Distributed computing improves:
A) Scalability and Reliability
B) Monitor Size
C) CPU Temperature
D) Keyboard Efficiency
Answer: A
195. Data-level parallelism operates on:
A) Multiple Data Elements Simultaneously
B) Single Data Only
C) Single Instruction Only
D) Cache Blocks
Answer: A
196. Instruction-level parallelism improves:
A) Instruction Execution Efficiency
B) Memory Capacity
C) Disk Size
D) Cache Replacement
Answer: A
197. Superscalar architecture exploits:
A) Instruction-Level Parallelism
B) Memory Management
C) Disk Scheduling
D) Virtualization
Answer: A
198. Multicore processors improve:
A) Parallel Execution
B) Cache Size Only
C) Memory Capacity Only
D) Bus Width Only
Answer: A
199. The main challenge in parallel computing is:
A) Synchronization and Communication
B) Monitor Resolution
C) Keyboard Design
D) Power Supply
Answer: A
200. Advanced computer architectures focus on:
A) Performance, Scalability, and Energy Efficiency
B) Larger Keyboards
C) Bigger Monitors
D) More Hard Disks Only
Answer: A
Computer Organization & Architecture (MCA 1st Semester)
MCQs 201–250
201. An instruction set is:
A) Collection of Instructions a CPU Can Execute
B) Collection of Memory Locations
C) Group of Registers
D) Set of Input Devices
Answer: A
202. Instruction set design affects:
A) Processor Performance
B) Software Compatibility
C) Hardware Complexity
D) All of these
Answer: D
203. Fixed-length instructions are commonly used in:
A) RISC Architectures
B) CISC Architectures
C) Analog Computers
D) Mainframes Only
Answer: A
204. Variable-length instructions are commonly used in:
A) RISC
B) CISC
C) SIMD
D) MISD
Answer: B
205. Orthogonal instruction sets provide:
A) Flexible Use of Instructions and Addressing Modes
B) Larger Monitors
C) Faster Keyboards
D) More Storage
Answer: A
206. Micro-operations are:
A) Elementary CPU Operations
B) Memory Units
C) Cache Blocks
D) Disk Operations
Answer: A
207. Register Transfer Language (RTL) is used to describe:
A) Data Transfers Between Registers
B) Disk Access
C) Networking Operations
D) Cache Mapping
Answer: A
208. Control signals are generated by:
A) Control Unit
B) ALU
C) Memory
D) Bus Controller Only
Answer: A
209. Hardwired control units are generally:
A) Faster but Less Flexible
B) Slower but More Flexible
C) Larger than Memory
D) Software Controlled
Answer: A
210. Microprogrammed control units are:
A) More Flexible
B) Easier to Modify
C) Based on Microinstructions
D) All of these
Answer: D
211. Pipeline speedup is ideally equal to:
A) Number of Pipeline Stages
B) Cache Size
C) CPU Frequency
D) Register Count
Answer: A
212. Pipeline stalls occur due to:
A) Hazards
B) Registers
C) Memory Size
D) I/O Devices
Answer: A
213. Operand forwarding helps reduce:
A) Data Hazards
B) Structural Hazards
C) Cache Misses
D) Interrupts
Answer: A
214. Speculative execution is used with:
A) Branch Prediction
B) Cache Mapping
C) RAID
D) DMA
Answer: A
215. Out-of-order execution improves:
A) Instruction-Level Parallelism
B) Memory Capacity
C) Bus Width
D) Disk Speed
Answer: A
216. In-order execution means:
A) Instructions Execute Sequentially
B) Instructions Execute Randomly
C) Multiple Instructions Execute Simultaneously
D) No Instruction Decoding
Answer: A
217. Superscalar processors contain:
A) Multiple Execution Units
B) One Register Only
C) One Pipeline Stage
D) No Cache
Answer: A
218. VLIW stands for:
A) Very Long Instruction Word
B) Virtual Long Instruction Word
C) Variable Length Instruction Word
D) Very Large Internal Word
Answer: A
219. VLIW architecture relies on:
A) Compiler Scheduling
B) Cache Mapping
C) DMA
D) Interrupts
Answer: A
220. Embedded systems are designed for:
A) Specific Applications
B) General Computing Only
C) Database Management Only
D) Networking Only
Answer: A
221. A microcontroller typically includes:
A) CPU
B) Memory
C) I/O Interfaces
D) All of these on a Single Chip
Answer: D
222. Which is commonly used in embedded systems?
A) ARM Processor
B) Supercomputer
C) Mainframe
D) RAID Controller
Answer: A
223. ARM architecture is known for:
A) Low Power Consumption
B) High Energy Usage
C) Large Instruction Size
D) No Registers
Answer: A
224. RISC-V is:
A) Open-Source ISA
B) Proprietary ISA
C) Memory Technology
D) Cache Architecture
Answer: A
225. One advantage of RISC-V is:
A) Extensibility
B) Open Standard
C) No Licensing Fees
D) All of these
Answer: D
226. Multicore processors improve:
A) Parallel Processing Capability
B) Monitor Resolution
C) Disk Storage
D) Keyboard Efficiency
Answer: A
227. NUMA stands for:
A) Non-Uniform Memory Access
B) Network Uniform Memory Access
C) Non-Universal Memory Architecture
D) Numerical Memory Access
Answer: A
228. In NUMA systems:
A) Memory Access Time Varies by Location
B) Memory Access Time is Always Same
C) No Shared Memory Exists
D) Cache is Disabled
Answer: A
229. UMA stands for:
A) Uniform Memory Access
B) Universal Memory Access
C) Unified Machine Access
D) User Memory Access
Answer: A
230. Symmetric multiprocessing generally uses:
A) UMA Architecture
B) NUMA Only
C) Virtual Memory Only
D) RAID Architecture
Answer: A
231. Power consumption in processors is mainly affected by:
A) Voltage
B) Frequency
C) Circuit Activity
D) All of these
Answer: D
232. Dynamic Voltage Scaling helps:
A) Reduce Power Consumption
B) Increase Cache Size
C) Increase Disk Space
D) Reduce Memory Capacity
Answer: A
233. Thermal management is important because:
A) Excess Heat Reduces Reliability
B) Increases Cache Size
C) Improves Disk Performance
D) Improves Keyboard Speed
Answer: A
234. Green computing aims to:
A) Improve Energy Efficiency
B) Increase Power Usage
C) Reduce Processor Performance
D) Eliminate Memory
Answer: A
235. Quantum computing uses:
A) Qubits
B) Bytes
C) Nibbles
D) Words
Answer: A
236. Superposition is a concept in:
A) Quantum Computing
B) Cache Memory
C) RAID
D) DMA
Answer: A
237. Quantum entanglement is:
A) Quantum Phenomenon
B) Memory Mapping Technique
C) Cache Policy
D) Bus Protocol
Answer: A
238. GPU acceleration is widely used in:
A) AI and Machine Learning
B) Graphics Rendering
C) Scientific Computing
D) All of these
Answer: D
239. Tensor Processing Units (TPUs) are optimized for:
A) Machine Learning Workloads
B) Disk Operations
C) Printing Tasks
D) Networking Only
Answer: A
240. Edge computing processes data:
A) Near the Data Source
B) Only in Cloud
C) Only in Main Memory
D) Only in Cache
Answer: A
241. Neuromorphic computing is inspired by:
A) Human Brain Structure
B) Hard Disk Design
C) Bus Architecture
D) Cache Memory
Answer: A
242. FPGA stands for:
A) Field Programmable Gate Array
B) Fast Programmable Gate Architecture
C) Flexible Program Gate Array
D) Field Processing Gate Array
Answer: A
243. FPGA devices are:
A) Reconfigurable Hardware
B) Fixed Hardware Only
C) Memory Devices
D) Storage Devices
Answer: A
244. ASIC stands for:
A) Application Specific Integrated Circuit
B) Advanced System Integrated Circuit
C) Application System Internal Circuit
D) Automated Specific Integrated Circuit
Answer: A
245. ASICs are optimized for:
A) Specific Applications
B) General-Purpose Computing
C) Database Storage
D) Networking Only
Answer: A
246. Modern processor design emphasizes:
A) Parallelism
B) Energy Efficiency
C) Scalability
D) All of these
Answer: D
247. The performance equation is:
A) CPU Time = Instruction Count × CPI × Clock Cycle Time
B) CPU Time = Memory × Cache
C) CPU Time = Registers × Bus Width
D) CPU Time = Frequency × Storage
Answer: A
248. Reducing CPI generally:
A) Improves Performance
B) Reduces Performance
C) Increases Memory Usage
D) Reduces Cache Size
Answer: A
249. Computer architecture continues to evolve because of:
A) Need for Higher Performance
B) Energy Constraints
C) New Applications
D) All of these
Answer: D
250. The ultimate goal of computer organization and architecture is:
A) Efficient, Reliable, and High-Performance Computing
B) Larger Monitors
C) More Keyboards
D) Bigger Printers
Answer: A
Computer Organization & Architecture (MCA 1st Semester)
MCQs 251–300
251. Cache coherence is concerned with:
A) Maintaining consistency among multiple caches
B) Increasing cache size
C) Reducing RAM size
D) Improving monitor resolution
Answer: A
252. Cache coherence problems occur mainly in:
A) Single Processor Systems
B) Multiprocessor Systems
C) Embedded Systems Only
D) Standalone Computers
Answer: B
253. MESI protocol is used for:
A) Cache Coherence
B) Memory Allocation
C) Disk Scheduling
D) Interrupt Handling
Answer: A
254. MESI stands for:
A) Modified, Exclusive, Shared, Invalid
B) Main, External, Shared, Internal
C) Memory, Execute, Store, Interrupt
D) Modified, Execute, Shared, Input
Answer: A
255. A bus snooping protocol is used in:
A) Cache Coherence Mechanisms
B) DMA Transfers
C) Virtual Memory
D) Disk Management
Answer: A
256. Mutual exclusion ensures:
A) Only One Process Accesses a Shared Resource at a Time
B) Multiple Processes Access Simultaneously
C) Faster Disk Access
D) More Cache Hits
Answer: A
257. A semaphore is used for:
A) Process Synchronization
B) Cache Mapping
C) Memory Refreshing
D) RAID Management
Answer: A
258. Deadlock occurs when:
A) Processes Wait Indefinitely for Resources
B) CPU Works Faster
C) Cache Miss Occurs
D) Memory Is Full
Answer: A
259. Scalability refers to:
A) Ability to Handle Increased Workload
B) Increasing Monitor Size
C) Reducing RAM
D) Expanding Keyboard Functions
Answer: A
260. Shared memory architecture allows:
A) Multiple Processors to Access Common Memory
B) One Processor Only
C) No Memory Sharing
D) Virtual Memory Only
Answer: A
261. Distributed memory architecture uses:
A) Separate Memory for Each Processor
B) Shared Cache Only
C) One Common Register
D) Single CPU
Answer: A
262. Interconnection networks connect:
A) Processors and Memory Modules
B) Keyboards and Monitors
C) Printers and Scanners
D) ROM and RAM Only
Answer: A
263. A crossbar switch provides:
A) High-Speed Interconnection
B) Memory Storage
C) Disk Access
D) Cache Replacement
Answer: A
264. Hypercube architecture is used in:
A) Parallel Computing Systems
B) Embedded Systems
C) Single-Core Systems
D) Printers
Answer: A
265. Parallel computers improve performance through:
A) Concurrent Execution
B) Increased Disk Size
C) Reduced RAM
D) Fewer Instructions
Answer: A
266. Granularity in parallel computing refers to:
A) Amount of Computation per Communication
B) Cache Size
C) Register Width
D) CPU Frequency
Answer: A
267. Fine-grained parallelism involves:
A) Frequent Communication Between Tasks
B) No Communication
C) Large Independent Tasks
D) Disk Operations Only
Answer: A
268. Coarse-grained parallelism involves:
A) Large Independent Tasks
B) Continuous Synchronization
C) Small Instructions Only
D) Cache Access Only
Answer: A
269. Branch prediction improves:
A) Pipeline Efficiency
B) Memory Capacity
C) Cache Size
D) Disk Performance
Answer: A
270. Static branch prediction:
A) Uses Fixed Rules
B) Learns from Execution History
C) Uses AI Models
D) Requires No Branches
Answer: A
271. Dynamic branch prediction:
A) Uses Runtime Information
B) Uses Fixed Rules Only
C) Uses No History
D) Is Not Used in Modern CPUs
Answer: A
272. A branch target buffer (BTB) stores:
A) Predicted Branch Addresses
B) Cache Data
C) Register Contents
D) Disk Blocks
Answer: A
273. Instruction-level parallelism (ILP) exploits:
A) Overlapping Instruction Execution
B) Memory Expansion
C) Disk Access
D) Cache Replacement
Answer: A
274. Data-level parallelism (DLP) is heavily used in:
A) Vector Processing
B) Keyboard Input
C) Disk Scheduling
D) DMA Operations
Answer: A
275. Thread-level parallelism (TLP) focuses on:
A) Concurrent Execution of Threads
B) Cache Mapping
C) Memory Allocation
D) Bus Control
Answer: A
276. SIMD instructions are especially useful for:
A) Multimedia Processing
B) Text Editing Only
C) Disk Formatting
D) Memory Refreshing
Answer: A
277. AVX instructions are examples of:
A) SIMD Extensions
B) Cache Protocols
C) Memory Controllers
D) RAID Standards
Answer: A
278. GPU architecture contains:
A) Many Small Processing Cores
B) One Large Core Only
C) No Cache
D) No Memory
Answer: A
279. CUDA is developed by:
A) NVIDIA
B) Intel
C) AMD
D) IBM
Answer: A
280. GPGPU stands for:
A) General-Purpose Computing on Graphics Processing Units
B) Graphics Processing General Unit
C) General Processor Graphics Unit
D) Graphics Parallel Processing Unit
Answer: A
281. Cloud data centers consist of:
A) Large Numbers of Servers
B) Single Computers
C) Only Mainframes
D) Only Embedded Devices
Answer: A
282. Virtualization enables:
A) Multiple Virtual Machines on One Physical Machine
B) Larger Monitors
C) More Keyboards
D) Faster Printers
Answer: A
283. A hypervisor manages:
A) Virtual Machines
B) Cache Memory
C) Registers
D) Disk Controllers
Answer: A
284. Type-1 hypervisor runs:
A) Directly on Hardware
B) On Top of an OS
C) Inside Cache
D) In ROM
Answer: A
285. Type-2 hypervisor runs:
A) On a Host Operating System
B) Directly on Hardware
C) Inside BIOS
D) In Cache
Answer: A
286. Examples of Type-1 hypervisors include:
A) VMware ESXi
B) Microsoft Hyper-V
C) Xen
D) All of these
Answer: D
287. Energy-efficient computing focuses on:
A) Reducing Power Consumption
B) Increasing Heat Generation
C) Reducing Performance Only
D) Eliminating Memory
Answer: A
288. Power-aware processor design aims to:
A) Balance Performance and Energy Use
B) Increase Voltage Only
C) Remove Cache
D) Eliminate Registers
Answer: A
289. Moore's Law states that:
A) Transistor Count Doubles Approximately Every Two Years
B) Memory Size Halves Every Year
C) CPUs Become Slower Over Time
D) Storage Cost Increases
Answer: A
290. Dennard Scaling is related to:
A) Power and Transistor Scaling
B) Cache Mapping
C) Virtual Memory
D) RAID Systems
Answer: A
291. Modern CPUs use multicore designs because:
A) Clock Frequency Scaling Has Limitations
B) RAM Is Expensive
C) Disks Are Slow
D) Keyboards Need More Power
Answer: A
292. Heterogeneous computing combines:
A) Different Types of Processing Units
B) Only CPUs
C) Only GPUs
D) Only Memory Units
Answer: A
293. CPU-GPU collaboration is common in:
A) AI and Scientific Applications
B) Text Editing Only
C) Disk Formatting
D) BIOS Programming Only
Answer: A
294. Exascale computing refers to systems capable of:
A) 10¹⁸ Operations Per Second
B) 10¹² Operations Per Second
C) 10⁶ Operations Per Second
D) 10⁹ Operations Per Second
Answer: A
295. Modern AI accelerators are designed for:
A) Matrix and Tensor Operations
B) Disk Scheduling
C) Cache Replacement
D) Keyboard Processing
Answer: A
296. Edge AI performs:
A) AI Processing Near Data Sources
B) AI Only in Cloud
C) AI Only in Supercomputers
D) AI Only in Mainframes
Answer: A
297. Quantum computers are expected to excel at:
A) Certain Specialized Problems
B) Word Processing Only
C) Basic Arithmetic Only
D) Disk Management Only
Answer: A
298. The future trend in architecture is:
A) Parallelism and Specialization
B) Single-Core Expansion
C) Removal of Cache
D) Elimination of Memory Hierarchy
Answer: A
299. Modern computer architecture aims to achieve:
A) High Performance, Reliability, and Efficiency
B) Larger Monitors
C) Bigger Keyboards
D) Fewer Instructions Only
Answer: A
300. Computer Organization and Architecture primarily focuses on:
A) Designing Efficient Computing Systems
B) Creating Web Pages
C) Managing Social Media
D) Editing Images
Answer: A
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